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PD - 94662
IRLR7807Z IRLU7807Z
Applications High Frequency Synchronous Buck Converters for Computer Processor Power Benefits Very Low RDS(on) at 4.5V VGS Ultra-Low Gate Impedance Fully Characterized Avalanche Voltage and Current
HEXFET(R) Power MOSFET
VDSS RDS(on) max Qg (typ.)
30V 13.8m 7.0nC
D-Pak IRLR7807Z
I-Pak IRLU7807Z
Absolute Maximum Ratings
Parameter
VDS VGS ID @ TC = 25C ID @ TC = 100C IDM PD @TC = 25C PD @TC = 100C TJ TSTG Drain-to-Source Voltage Gate-to-Source Voltage Continuous Drain Current, VGS @ 10V Continuous Drain Current, VGS @ 10V Pulsed Drain Current Maximum Power Dissipation Maximum Power Dissipation Linear Derating Factor Operating Junction and Storage Temperature Range Soldering Temperature, for 10 seconds 300 (1.6mm from case)
Max.
30 20 43 30 170 40 20 0.27 -55 to + 175
Units
V
A W
W/C C
Thermal Resistance
Parameter
RJC RJA RJA Junction-to-Case Junction-to-Ambient (PCB Mount) Junction-to-Ambient
Typ.
--- --- ---
Max.
3.75 50 110
Units
C/W
Notes
through
are on page 11
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1
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IRLR/U7807Z
Static @ TJ = 25C (unless otherwise specified)
Parameter
BVDSS VDSS/TJ RDS(on) VGS(th) VGS(th)/TJ IDSS IGSS gfs Qg Qgs1 Qgs2 Qgd Qgodr Qsw Qoss td(on) tr td(off) tf Ciss Coss Crss Drain-to-Source Breakdown Voltage Breakdown Voltage Temp. Coefficient Static Drain-to-Source On-Resistance Gate Threshold Voltage Gate Threshold Voltage Coefficient Drain-to-Source Leakage Current Gate-to-Source Forward Leakage Gate-to-Source Reverse Leakage Forward Transconductance Total Gate Charge Pre-Vth Gate-to-Source Charge Post-Vth Gate-to-Source Charge Gate-to-Drain Charge Gate Charge Overdrive Switch Charge (Qgs2 + Qgd) Output Charge Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time Input Capacitance Output Capacitance Reverse Transfer Capacitance
Min. Typ. Max. Units
30 --- --- --- 1.35 --- --- --- --- --- 51 --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- 23 11 14.5 1.8 -4.5 --- --- --- --- --- 7.0 1.8 0.7 2.7 1.8 3.4 4.0 7.1 28 9.8 3.5 780 180 100 --- --- V
Conditions
VGS = 0V, ID = 250A
mV/C Reference to 25C, ID = 1mA m VGS = 10V, ID = 15A 13.8 18.2 2.25 --- 1.0 150 100 -100 --- 11 --- --- --- --- --- --- --- --- --- --- --- --- --- pF VGS = 0V VDS = 15V = 1.0MHz ns nC VDS = 15V, VGS = 0V VDD = 15V, VGS = 4.5V ID = 12A Clamped Inductive Load nC VDS = 15V VGS = 4.5V ID = 12A See Fig. 16 S nA V mV/C A VDS = 24V, VGS = 0V VDS = 24V, VGS = 0V, TJ = 125C VGS = 20V VGS = -20V VDS = 15V, ID = 12A VGS = 4.5V, ID = 12A VDS = VGS, ID = 250A
Avalanche Characteristics
EAS IAR EAR Parameter Single Pulse Avalanche Energy Avalanche Current Repetitive Avalanche Energy Typ. --- --- --- Max. 28 12 4.0 Units mJ A mJ
Diode Characteristics
Parameter
IS ISM VSD trr Qrr ton Continuous Source Current (Body Diode) Pulsed Source Current (Body Diode) Diode Forward Voltage Reverse Recovery Time Reverse Recovery Charge Forward Turn-On Time
Min. Typ. Max. Units
--- --- --- --- --- --- --- --- 23 14 43 A 170 1.0 35 21 V ns nC
Conditions
MOSFET symbol showing the integral reverse p-n junction diode. TJ = 25C, IS = 12A, VGS = 0V TJ = 25C, IF = 12A, VDD = 15V di/dt = 100A/s
Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD)
2
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IRLR/U7807Z
1000
TOP
VGS
1000
VGS
ID, Drain-to-Source Current (A)
ID, Drain-to-Source Current (A)
100
10
10V 5.0V 4.5V 3.5V 3.0V 2.7V 2.5V BOTTOM 2.25V
100
10V 5.0V 4.5V 3.5V 3.0V 2.7V 2.5V BOTTOM 2.25V
TOP
1
10
0.1
2.5V
0.01
1
2.5V 20s PULSE WIDTH Tj = 175C
20s PULSE WIDTH Tj = 25C
0.001 0.1 1 10
0.1 0.1 1 10
VDS, Drain-to-Source Voltage (V)
VDS, Drain-to-Source Voltage (V)
Fig 1. Typical Output Characteristics
Fig 2. Typical Output Characteristics
1000.0
2.0
RDS(on) , Drain-to-Source On Resistance (Normalized)
ID = 30A VGS = 10V
ID, Drain-to-Source Current ()
T J = 25C T J = 175C
100.0
1.5
10.0
1.0
1.0
VDS = 10V 20s PULSE WIDTH
0.1 2.0 3.0 4.0 5.0 6.0 7.0 8.0 9.0
0.5 -60 -40 -20 0 20 40 60 80 100 120 140 160 180
VGS, Gate-to-Source Voltage (V)
T J , Junction Temperature (C)
Fig 3. Typical Transfer Characteristics
Fig 4. Normalized On-Resistance vs. Temperature
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IRLR/U7807Z
10000 VGS = 0V, f = 1 MHZ C iss = C gs + C gd, C ds C rss = C gd C oss = C ds + C gd SHORTED
12 ID= 12A
VGS, Gate-to-Source Voltage (V)
10
VDS= 24V VDS= 15V
C, Capacitance (pF)
1000
Ciss
8
Coss
100
6
Crss
4
2
10 1 10 100
0 0 4 8 12 16
VDS, Drain-to-Source Voltage (V)
QG Total Gate Charge (nC)
Fig 5. Typical Capacitance vs. Drain-to-Source Voltage
Fig 6. Typical Gate Charge vs. Gate-to-Source Voltage
1000.0
1000
OPERATION IN THIS AREA LIMITED BY R DS(on)
ISD, Reverse Drain Current (A)
100.0 T J = 175C 10.0
ID, Drain-to-Source Current (A)
100
10
100sec
1.0 T J = 25C VGS = 0V 0.1 0.0 0.5 1.0 1.5 2.0 VSD, Source-toDrain Voltage (V)
1 Tc = 25C Tj = 175C Single Pulse 0.1 0.1 1.0 10.0
1msec
10msec
100.0
1000.0
VDS , Drain-toSource Voltage (V)
Fig 7. Typical Source-Drain Diode Forward Voltage
Fig 8. Maximum Safe Operating Area
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IRLR/U7807Z
50 LIMITED BY PACKAGE 40
ID , Drain Current (A)
2.5
VGS(th) Gate threshold Voltage (V)
2.0
30
ID = 250A
20
1.5
10
0 25 50 75 100 125 150 175 T C , Case Temperature (C)
1.0 -75 -50 -25 0 25 50 75 100 125 150 175
T J , Temperature ( C )
Fig 9. Maximum Drain Current vs. Case Temperature
Fig 10. Threshold Voltage vs. Temperature
10
Thermal Response ( Z thJC )
D = 0.50
1
0.20 0.10 0.05
R1 R1 J 1 2 R2 R2 R3 R3 3 C 3
0.1
0.02 0.01
J
Ri (C/W) i (sec) 1.796 0.000267 1.112 0.842 0.000607 0.004249
1
2
0.01
SINGLE PULSE ( THERMAL RESPONSE )
Ci= i/Ri Ci i/Ri
Notes: 1. Duty Factor D = t1/t2 2. Peak Tj = P dm x Zthjc + Tc
0.0001 0.001 0.01 0.1
0.001 1E-006 1E-005
t1 , Rectangular Pulse Duration (sec)
Fig 11. Maximum Effective Transient Thermal Impedance, Junction-to-Case
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IRLR/U7807Z
15V
120
EAS, Single Pulse Avalanche Energy (mJ)
TOP
VDS
L
DRIVER
100
BOTTOM
ID 3.0A 1.4A 12A
RG
VGS 20V
D.U.T
IAS tp
+ V - DD
80
A
0.01
60
Fig 12a. Unclamped Inductive Test Circuit
V(BR)DSS tp
40
20
0 25 50 75 100 125 150 175
Starting T J, Junction Temperature (C)
Fig 12c. Maximum Avalanche Energy Vs. Drain Current
I AS
LD VDS
VDS
90%
+
VDD -
Fig 12b. Unclamped Inductive Waveforms
10%
D.U.T
Current Regulator Same Type as D.U.T.
VGS
VGS Pulse Width < 1s Duty Factor < 0.1%
td(on)
50K 12V .2F .3F
Fig 14a. Switching Time Test Circuit
D.U.T. + V - DS
VGS
3mA
IG
ID
Current Sampling Resistors
Fig 13. Gate Charge Test Circuit
Fig 14b. Switching Time Waveforms
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IRLR/U7807Z
Driver Gate Drive
D.U.T
+
Circuit Layout Considerations * Low Stray Inductance * Ground Plane * Low Leakage Inductance Current Transformer
Reverse Recovery Current
P.W.
Period
D=
P.W. Period VGS=10V
*
+
D.U.T. ISD Waveform Body Diode Forward Current di/dt D.U.T. VDS Waveform Diode Recovery dv/dt
-
-
+
VDD
RG
* * * *
dv/dt controlled by RG Driver same type as D.U.T. ISD controlled by Duty Factor "D" D.U.T. - Device Under Test
VDD
+ -
Re-Applied Voltage Inductor Curent
Body Diode
Forward Drop
Ripple 5%
ISD
* VGS = 5V for Logic Level Devices Fig 15. Peak Diode Recovery dv/dt Test Circuit for N-Channel HEXFET(R) Power MOSFETs
Id Vds Vgs
Vgs(th)
Qgs1 Qgs2
Qgd
Qgodr
Fig 16. Gate Charge Waveform
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IRLR/U7807Z
Power MOSFET Selection for Non-Isolated DC/DC Converters
Control FET Special attention has been given to the power losses in the switching elements of the circuit - Q1 and Q2. Power losses in the high side switch Q1, also called the Control FET, are impacted by the Rds(on) of the MOSFET, but these conduction losses are only about one half of the total losses. Power losses in the control switch Q1 are given by; Synchronous FET The power loss equation for Q2 is approximated by;
* P =P loss conduction + P drive + P output
P = Irms x Rds(on) loss
+ (Qg x Vg x f )
(
2
)
Ploss = Pconduction+ Pswitching+ Pdrive+ Poutput
This can be expanded and approximated by;
Q + oss x Vin x f + (Qrr x Vin x f ) 2
*dissipated primarily in Q1.
Ploss = (Irms x Rds(on ) )
2
Qgs2 Qgd +Ix x Vin x f + I x x Vin x ig ig + (Qg x Vg x f ) + Qoss x Vin x f 2
f
This simplified loss equation includes the terms Qgs2 and Qoss which are new to Power MOSFET data sheets. Qgs2 is a sub element of traditional gate-source charge that is included in all MOSFET data sheets. The importance of splitting this gate-source charge into two sub elements, Qgs1 and Qgs2, can be seen from Fig 16. Qgs2 indicates the charge that must be supplied by the gate driver between the time that the threshold voltage has been reached and the time the drain current rises to Idmax at which time the drain voltage begins to change. Minimizing Qgs2 is a critical factor in reducing switching losses in Q1. Qoss is the charge that must be supplied to the output capacitance of the MOSFET during every switching cycle. Figure A shows how Qoss is formed by the parallel combination of the voltage dependant (nonlinear) capacitance's Cds and Cdg when multiplied by the power supply input buss voltage.
For the synchronous MOSFET Q2, Rds(on) is an important characteristic; however, once again the importance of gate charge must not be overlooked since it impacts three critical areas. Under light load the MOSFET must still be turned on and off by the control IC so the gate drive losses become much more significant. Secondly, the output charge Qoss and reverse recovery charge Qrr both generate losses that are transfered to Q1 and increase the dissipation in that device. Thirdly, gate charge will impact the MOSFETs' susceptibility to Cdv/dt turn on. The drain of Q2 is connected to the switching node of the converter and therefore sees transitions between ground and Vin. As Q1 turns on and off there is a rate of change of drain voltage dV/dt which is capacitively coupled to the gate of Q2 and can induce a voltage spike on the gate that is sufficient to turn the MOSFET on, resulting in shoot-through current . The ratio of Qgd/Qgs1 must be minimized to reduce the potential for Cdv/dt turn on.
Figure A: Qoss Characteristic
8
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IRLR/U7807Z
D-Pak (TO-252AA) Package Outline
Dimensions are shown in millimeters (inches)
6.73 (.265) 6.35 (.250) -A5.46 (.215) 5.21 (.205) 4 1.27 (.050) 0.88 (.035)
2.38 (.094) 2.19 (.086)
1.14 (.045) 0.89 (.035) 0.58 (.023) 0.46 (.018)
6.45 (.245) 5.68 (.224) 6.22 (.245) 5.97 (.235) 1.02 (.040) 1.64 (.025) 1 2 3 0.51 (.020) MIN. 10.42 (.410) 9.40 (.370)
LEAD ASSIGNMENTS 1 - GATE 2 - DRAIN 3 - SOURCE 4 - DRAIN
-B1.52 (.060) 1.15 (.045) 3X 2X 1.14 (.045) 0.76 (.030) 0.89 (.035) 0.64 (.025) 0.25 (.010) M AMB
0.58 (.023) 0.46 (.018)
2.28 (.090) 4.57 (.180)
NOTES: 1 DIMENSIONING & TOLERANCING PER ANSI Y14.5M, 1982. 2 CONTROLLING DIMENSION : INCH. 3 CONFORMS TO JEDEC OUTLINE TO-252AA. 4 DIMENSIONS SHOWN ARE BEFORE SOLDER DIP, SOLDER DIP MAX. +0.16 (.006).
D-Pak (TO-252AA) Part Marking Information
Notes: This part marking information applies to devices produced before 02/26/2001
EXAMPLE: THIS IS AN IRFR120 WITH ASSEMBLY LOT CODE 9U1P
INTERNATIONAL RECTIFIER LOGO
IRFU120 9U 016 1P
DATE CODE YEAR = 0 WEEK = 16
ASSEMBLY LOT CODE
Notes: This part marking information applies to devices produced after 02/26/2001
EXAMPLE: THIS IS AN IRFR120 WITH ASSEMBLY LOT CODE 1234 ASSEMBLED ON WW 16, 1999 IN THE ASSEMBLY LINE "A" PART NUMBER INTERNATIONAL RECTIFIER LOGO
IRFU120 12 916A 34
ASSEMBLY LOT CODE
DATE CODE YEAR 9 = 1999 WEEK 16 LINE A
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IRLR/U7807Z
I-Pak (TO-251AA) Package Outline
Dimensions are shown in millimeters (inches)
6.73 (.265) 6.35 (.250) -A5.46 (.215) 5.21 (.205) 4 6.45 (.245) 5.68 (.224) 1.52 (.060) 1.15 (.045) 1 -B2.28 (.090) 1.91 (.075) 9.65 (.380) 8.89 (.350) 2 3 6.22 (.245) 5.97 (.235) 1.27 (.050) 0.88 (.035) 2.38 (.094) 2.19 (.086) 0.58 (.023) 0.46 (.018) LEAD ASSIGNMENTS 1 - GATE 2 - DRAIN 3 - SOURCE 4 - DRAIN
NOTES: 1 DIMENSIONING & TOLERANCING PER ANSI Y14.5M, 1982. 2 CONTROLLING DIMENSION : INCH. 3 CONFORMS TO JEDEC OUTLINE TO-252AA. 4 DIMENSIONS SHOWN ARE BEFORE SOLDER DIP, SOLDER DIP MAX. +0.16 (.006).
3X
1.14 (.045) 0.76 (.030)
3X
0.89 (.035) 0.64 (.025) M AMB
1.14 (.045) 0.89 (.035) 0.58 (.023) 0.46 (.018)
2.28 (.090) 2X
0.25 (.010)
I-Pak (TO-251AA) Part Marking Information
Notes: This part marking information applies to devices produced before 02/26/2001
EXAMPLE: THIS IS AN IRFR120 WITH ASSEMBLY LOT CODE 9U1P INTERNATIONAL RECTIFIER LOGO DATE CODE YEAR = 0 WEEK = 16
IRFU120 016 9U 1P
ASSEMBLY LOT CODE
Notes: This part marking information applies to devices produced after 02/26/2001
EXAMPLE: THIS IS AN IRFR120 WITH ASSEMBLY LOT CODE 5678 ASSEMBLED ON WW 19, 1999 IN THE ASSEMBLY LINE "A" INTERNATIONAL RECTIFIER LOGO PART NUMBER
IRFU120 919A 56 78
ASSEMBLY LOT CODE
DATE CODE YEAR 9 = 1999 WEEK 19 LINE A
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IRLR/U7807Z
D-Pak (TO-252AA) Tape & Reel Information
Dimensions are shown in millimeters (inches)
TR TRR TRL
16.3 ( .641 ) 15.7 ( .619 )
16.3 ( .641 ) 15.7 ( .619 )
12.1 ( .476 ) 11.9 ( .469 )
FEED DIRECTION
8.1 ( .318 ) 7.9 ( .312 )
FEED DIRECTION
NOTES : 1. CONTROLLING DIMENSION : MILLIMETER. 2. ALL DIMENSIONS ARE SHOWN IN MILLIMETERS ( INCHES ). 3. OUTLINE CONFORMS TO EIA-481 & EIA-541.
13 INCH
16 mm NOTES : 1. OUTLINE CONFORMS TO EIA-481.
Notes: Repetitive rating; pulse width limited by max. junction temperature. Starting TJ = 25C, L = 0.39mH, RG = 25, IAS = 12A. Pulse width 400s; duty cycle 2%. Calculated continuous current based on maximum allowable junction temperature. Package limitation current is 30A. When mounted on 1" square PCB (FR-4 or G-10 Material). For recommended footprint and soldering techniques refer to application note #AN-994.
Data and specifications subject to change without notice. This product has been designed and qualified for the Industrial market. Qualification Standards can be found on IR's Web site.
IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105 TAC Fax: (310) 252-7903 Visit us at www.irf.com for sales contact information.4/03
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